1. Field of the Invention
The present invention relates to an interpolator increasing the output word rate of a digital signal by interleaving words between successive input words . . . , Si, Si+1, . . . , the values of the interleaved output words depending on the difference between successive input words.
2. Description of the Prior Art
An interpolator of this type, which may be used in telephone line circuits, is included for instance as one of those part of the converter circuit disclosed in the European patent application published under No. 0234666 (P. Reusens et al 1-1), i.e. that immediately preceding a digital sigma-delta modulator. Basically, this particular interpolator receives 17-bit words at 32 kHz, these being rounded to 16-bit at the input of the interpolator which outputs words at 8.times.32=256 kHz by repeatedly storing the difference between two successive input words Si and Si+i in a hold register for a sampling period of 1000/32=31.25 microsecond and outputting linearly incremented words Si+(Si+1-Si)/8, Si+2(Si+1-Si)/8, . . . , Si+8(Si+1-Si)/8=Si+1 whereafter the difference Si+1-Si is replaced by that between the next pair, i.e. Si+2-Si+1. In principle, this linear interpolation involves a digital integrator with an input adder fed by (Si+1-Si)/8 at its first input and by the interpolator output Si, Si+(Si+1-Si)/8, . . . at its second input. The first input receives (Si+1-Si)/8 from Si+1-Si stored in the hold register due to the bits being shifted by 3 stages in a shift register, this division by 8 also converting the 16-bit into 19-bit words by the addition of 000 as Most Significant Bits of the words. The second input receives the successive interpolator output words Si, Si+(Si+1-Si)/8, . . . through a delay circuit of 1000/(32.times.8)=3.90625 microsecond corresponding to the 256 kHz output rate, i.e. one eighth of the sampling period. Every 31.25 microsecond, a sampling gate connects the output to an adder preceding the hold register and receiving the input words at its other input so that Si+2-Si+1 can replace Si+1-Si in the register. Operations are algebraic since Si+1-Si as well as Si, Si+1 can be positive or negative binary numbers.
Such a straight line interpolator where the increment is also obtained by division, using delay and recirculation circuits, was already disclosed in U.S. Pat. No. 4109110 (M. Gingell 12). As opposed to inserting N-1 words equal to the previous input word between the latter and the next, this was noted to double the attenuation (with peaks at the sampling frequency and all its harmonics), i.e. an equivalent spectrum filtering of G**2 where ** indicates that the preceding value is to be raised to the succeding exponent and where EQU G=(1-z**(-N))(1-z**(-1))**(-1)
This G value for the insertion of N-1 equal samples was indicated to correspond to the insertion of N-1 zero value samples followed by digital filtering at N times the sampling frequency.
In practice, the incrementation implying divisions of multibit numbers, means must be found to carry this out in an efficient manner and in that particular interpolator disclosed in the U.S. Pat. No. 4270026 (K. Shenoi et al 3-3) which uses a low pass digital recursive filter with integral powers of 2 for its coefficients one can perform divisions by integral powers of 2 without resorting to multibit multipliers. That interpolator operates at a much higher relative speed since the words received at 32 kHz are first loaded in parallel into an accumulator from which they are extracted by strobe pulses at 32.times.32=1024 kHz but with the 32 output words during each period of 31.25 microsecond including 3 zero words interleaved after each of the 8 words corresponding to the stored input word. The recursive filter fed with such output words includes dividers by 16 and 32 as part of the circuits needed to provide a suitable filter output at 32.times.8=256 kHz. Both dividers, that by 32 immediately preceding the filter output, are part of the recursive filter designed to provide at its output a suitably filtered signal at an increased word rate with those interleaved zero words between the last version of a repeated input sample and the first version of the next repeated input sample now being suitable interpolated values. The divisions by 16 and 32 may occur by shifting the binary words in the shift registers by 4 and 5 stages respectively and in order to avoid the complexities of divisions producing quotients with fractional parts, the recursive filter uses dividers storing the 4 and 5 Least Significant Bits remainders which are subsequently added to the next word to be divided. Indeed, this approximation technique was shown to give sufficiently accurate results, i.e. noise spectrum reshaping. Such dividers thus imply that the 16-bit input words become respectively 12 and 11-bit words at the output of the respective divider, due to the 4 and 5 LSB being saved for the next division, and with a recursive filters these 12 and 11 MSB are both fed back to the input of the filter for subtraction from the 16-bit input words.
The above binary division technique need not be restricted to interpolators involving recursive filter (with feedback) since instead of such Infinite Impulse Response filters, Finite Impulse Response or transversal filters avoided in the above US patent can also be used as disclosed in the IEEE Journal of Solid-State Circuits, Vol. SC-20, No 3, June 1985, p. 679 to 687. Therein, starting from Pulse Code Modulation words received at 8 kHz, first one interpolates to 32 kHz by duplicating each input word and each time interleaving a zero word between two successive input words, low pass filter sections following this to feed further cascaded interpolators to reach a 256 Khz and finally a 1024 kHz rate. While this last is obtained by a 4-tap rectangular window realized by oversampling, the intermediate interpolation from 32 to 256 Khz again involves divisions by integral powers of 2. This is achieved by a triangular window FIR filter built around a 16-bit accumulator clocked at 1 MHz (1024 kHz) and, as in the above European application, the difference between the input and output words is latched into a hold register. The 16-bit word stored during 31.25 microsecond is divided by 64 and then integrated at 256 kHz. As in the above US patent, the 6 LSB constituting the remainder of the division by 64 are saved for the next division of the stored 16-bit word while the 10 MSB are integrated at 256 Khz to produce 13-bit words due to the difference in input and output rates. In addition to the 13-bit words being repeated 4 times by the 4-point rectangular window FIR filter constituting the third cascaded interpolator, in the second, every 8 output samples these 13-bit words are fed back to the input, this at the 256/8=32 kHz rate to be subtracted from the input word so that a new increment can be stored in the hold register. The feedback circuit includes a shift register whereby these 13-bit words can be shifted by 3 stages to produce 16-bit words after a multiplication by 8. This operation is performed in a cycle distinct from that used to add the 6 LSB remainder (fractional) part to the next 16-bit word to be divided by 64 since the accumulator is only 16 bit wide
Thus, the interpolator defined at the beginning of this description can be built in a variety of ways relying on binary divisions but while the complexity of these can be advantageously reduced, as disclosed in the above U.S. Pat. No. 4,270,026, nevertheless the circuitry is still relatively complex, e.g. the IIR filter of this U.S. patent.